1. Field of the Invention
The present invention relates to a signal delay circuit, constituted by using a charge pump circuit, for delaying an input signal by a predetermined period and outputting the signal.
2. Description of the Related Art
A signal delay circuit for delaying an input clock signal by a predetermined period, a frequency multiplier for outputting a clock signal having a frequency twice that of an input clock signal, and a voltage-controlled oscillator (to be referred to as a VCO hereinafter) for outputting a clock signal having a frequency corresponding to a control voltage are formed in a semiconductor integrated circuit as needed.
A conventional signal delay circuit is constituted by using elements such as resistors or capacitors. The values of these resistors or capacitors change in accordance with variations in process parameters in the manufacture. Therefore, in the conventional signal delay circuit, a signal delay amount is not uniformly determined. In addition, a conventional frequency multiplier utilizes a signal delay amount produced by a circuit using an inverter and a capacitor. This signal delay amount changes in accordance with the characteristics of the inverter or the value of the capacitor. The characteristics of the inverter also depend on a power source voltage or an ambient temperature. Therefore, since the delay amount is not uniformly determined, lengths of "H"- and "L"-level periods vary. In the worst case, a so-called glitch having almost no "H"- or "L"-level period is generated, or only the "H" or "L" level sometimes continues. In a conventional VCO, a gate length, a threshold voltage, a gate oxide film thickness, and the like of each transistor constituting the VCO vary as process parameters vary in the manufacture. Therefore, an oscillation center frequency largely varies.